1. Field of the Invention
The present invention generally relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors having a channel region with a specified intrinsic stress to improve the charge carrier mobility.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors and resistors. These elements are connected internally to form complex circuits, such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements in the circuit in order to increase their functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit, and also reduces signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.
Field effect transistors are used as switching elements in integrated circuits. They allow control of a current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. In N-type transistors, the source and drain regions are doped with an N-type dopant. Conversely, in P-type transistors, the source and drain regions are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source region and the drain region. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
When reducing the size of field effect transistors, it is important to maintain a high conductivity of the channel region in the “on” state. The conductivity of the channel region in the “on” state depends on the dopant concentration in the channel region, the mobility of the charge carriers, the extension of the channel region in the width direction of the transistor and the distance between the source region and the drain region, which is commonly denoted as “channel length.” While a reduction of the width of the channel region leads to a decrease of the channel conductivity, a reduction of the channel length enhances the channel conductivity. An increase of the charge carrier mobility leads to an increase of the channel conductivity.
As feature sizes are reduced, the extension of the channel region in the width direction is also reduced. A reduction of the channel length entails a plurality of issues associated therewith. First, advanced techniques of photolithography and etching have to be provided in order to reliably and reproducibly create transistors having short channel lengths. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the source region and in the drain region in order to provide a low sheet resistivity and a low contact resistivity in combination with a desired channel controllability.
In view of the problems associated with a further reduction of the channel length, it has been proposed to also enhance the performance of field effect transistors by increasing the charge carrier mobility in the channel region. In principle, at least two approaches may be used to increase the charge carrier mobility.
First, the dopant concentration in the channel region may be reduced. Thus, the probability of scattering events of charge carriers in the channel region is reduced, which leads to an increase of the conductivity of the channel region. Reducing the dopant concentration in the channel region, however, significantly affects the threshold voltage of the transistor device. This makes the reduction of dopant concentration a less attractive approach.
Second, the lattice structure in the channel region may be modified by creating tensile or compressive strain. This leads to a modified mobility of electrons and holes, respectively. Depending on the magnitude of the strain, a biaxial tensile strain may increase the mobility of electrons in a silicon layer on an insulating substrate or a substrate comprising an insulating layer provided under the silicon layer by up to 300%, and may also increase the hole mobility when above a 30% SiGe equivalent level. The mobility of holes may also be increased by providing a silicon layer having a compressive strain.
A method of forming a filed effect transistor wherein the channel region is formed in a strained silicon layer provided on an insulating layer will be described in the following with reference to FIGS. 1a-1f. 
FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of the prior art manufacturing process. A substrate 101, which may, for example, comprise a silicon wafer, is provided. On the substrate, a layer 102 of an insulating material is formed, for example by means of known methods of deposition and/or oxidation. In some examples of prior art processes, the layer 102 of insulating material may comprise silicon dioxide.
In addition to the substrate 101, an auxiliary substrate 103, which is shown in FIG. 1b, is provided. On the auxiliary substrate 103, a strain-creating layer 104 and a layer 105 of a semiconductor material are formed. This may be done by means of known deposition techniques such as chemical vapor deposition and/or plasma enhanced chemical vapor deposition. The layer 105 of semiconductor material may comprise silicon.
The strain-creating layer 104 comprises a material having a lattice constant other than the lattice constant of the semiconductor material 105. When the semiconductor material of the layer 105 is deposited on the strain-creating layer 104, the crystalline structure of the semiconductor material 105 is influenced by the crystal lattice of the strain-creating layer 104. Thus, a global biaxial strain can be created in the layer 105 of semiconductor material.
If the lattice constant of the material of the strain-creating layer 104 is greater than the lattice constant which the semiconductor material of the layer 105 adopts in a bulk crystal, the atoms in the layer 105 arrange at a greater distance than in a bulk crystal of the semiconductor material. Thus, the layer 105 of semiconductor material comprises a tensile strain. Conversely, if the lattice constant of the material of the strain-creating layer 104 is smaller than that of the semiconductor material of layer 105 in a bulk crystal, the layer 105 of semiconductor material is formed with an intrinsic compressive strain. In examples of prior art processes wherein the layer 105 of semiconductor material comprises silicon, a strain-creating layer 104 comprising an alloy of silicon and germanium may be used to create a tensile strain. In order to create a compressive strain in the layer 105 when comprising silicon, the strain-creating layer 104 may be made of an alloy of silicon and carbon.
The auxiliary substrate 103 is bonded to the substrate 101. To this end, the auxiliary substrate 103 and the substrate 101 are arranged such that the layer 105 of semiconductor material and the layer 102 of insulating material contact each other, as shown in FIG. 1c. Then, a known bonding technique, such as anodic bonding, is employed to fix the layer 105 of semiconductor material to the layer 102 of insulating material.
A schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process according to the state of the art is shown in FIG. 1d. The auxiliary substrate 103 and the strain-creating layer 104 are removed, for example by means of grinding, etching or delamination. Then, the substrate 101 comprises on its surface the layer 105 of semiconductor material over the layer 102 of insulating material. The biaxial strain in the layer 105 of semiconductor material, which has been induced by the presence of the strain-creating layer 104 in the formation of the layer 105, is substantially preserved after the removal of the strain-creating layer 104. Therefore, the layer 105 of semiconductor material still comprises a biaxial strain.
A schematic cross-sectional view of the semiconductor structure 100 in a further stage of the manufacturing process according to the state of the art is shown in FIG. 1e. Shallow trench isolations 106, 107 which may be part of one continuous trench isolation structure are formed in the layer 105 of semiconductor material. The shallow trench isolations 106, 107 and the layer 102 of insulating material insulate a portion of the layer 105 of semiconductor material from the rest of the layer 105. Then, an active region 181 is created in the region between the shallow trench isolations 106, 107, for example by means of a known ion implantation process, wherein ions of a dopant material are introduced into the layer 105 of semiconductor material.
Subsequently, a gate electrode 109, which is separated from the active region 181 by a gate insulation layer 108, is formed over the active region. In the formation of the gate electrode 109 and the gate insulation layer 108, as well as in the formation of the shallow trench isolations 106, 107, techniques known to persons skilled in the art, such as advanced methods of deposition, photolithography, etching and oxidation, may be employed.
After the formation of the gate electrode 109, the semiconductor structure 100 is irradiated with ions 110 of a dopant material, which are indicated by arrows in FIG. 1e. The ions impinge on the layer 105 of semiconductor material and penetrate the layer 105 of semiconductor material. Thus, dopant material is introduced into the layer 105 of semiconductor material to form an extended source region 111 and an extended drain region 112. The gate electrode 109 absorbs ions impinging thereon such that substantially no dopant material is introduced into a channel region 123 below the gate electrode 109. The impact of the ions removes atoms of the semiconductor material in the layer 105 from their sites in the strained crystal lattice. At typical ion doses used in advanced methods of manufacturing a field effect transistor, the semiconductor material in the extended source region 111 and the extended drain region 112 is amorphized.
A further stage of the manufacturing process according to the state of the art is shown in FIG. 1f. Sidewall spacers 119, 120 are formed adjacent the gate electrode 109, which may be done by means of well-known methods comprising an isotropic deposition of a layer of a sidewall spacer material and an anisotropic etching process. Then, a further ion implantation, as indicated by arrows 190 in FIG. 1f, is performed to create a source region 113 and a drain region 114. Similar to the formation of the extended source region 111 and the extended drain region 112, the ion implantation into the source region 113 and the drain region 114 may lead to an amorphization of the semiconductor material 105. Finally, an annealing process may be performed to re-crystallize the semiconductor material 105 in the source region 113, the drain region 114, the extended source region 111 and the extended drain region 112.
A problem of the method of forming a field effect transistor according to the state of the art is that the strain-induced enhancement of the mobility of electrons and/or holes in the channel region is significantly reduced at short channel lengths. While in transistors having a relatively large channel length considerably greater than about 50 nm or more, an increase of the drive current by up to 100% may be obtained, in transistors having a relatively short channel length of about 50 nm or less, only an increase of the transistor drive current of about 5-10% is observed.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.